This invention relates generally to signal processing and more particularly to analog delay lines.
Analog delay lines are important building blocks in many signal processing applications. Both continuous time and discrete time circuits have been used for these delay lines. The discrete delay lines have many advantages over the continuous delay lines in mixed-mode integrated circuit environments. The discreet time delay lines may be implemented in either switch or capacitor (SC) circuits or switch current (SI) circuits.
FIG. 1 shows a commonly used prior are SC delay line with op-amp offset and gain compensation. Each delay stage, which includes one op-amp, one capacitor and three switches, achieves a one-half clock cycle delay. A disadvantage of the design used in FIG. 1 is that it requires op-amps in the intermediate delay stages, which consume both die area and power. Moreover, the achievable sampling speed is limited by the speed of the op-amps.
In many applications where intermediate delayed signals are not needed for output, the op-amps can be removed except for the op-amp stage. The resulting delay lines are commonly referred to as "quasi-passive" SC delay lines. An example of a prior art quasi-passive SC delay line is shown in FIG. 2. An input signal V.sub.IN is written into each capacitor sequentially and read out N-1 clock phases later, where N is the total number of delay stages. Another important advantage of this type of circuit over the one shown in FIG. 1 is that the effective sampling rate can be twice the system clock frequency. The increased sampling rate is accomplished by using both the rising and falling edges of the clock. The increased effective sampling rate reduces signal aliasing and the requirements of an anti-aliasing filter (not shown). The effective delay produced by the quasi-passive SC delay line is (N-1)/2.times.F where F is the system clock frequency.
One disadvantage of this circuit is that it requires even duty cycle, non-overlapping clock phases. The clock phases must be non-overlapping because the transistors in each stage e.g., Q1 and Q2 are controlled by adjacent clock phases. If the adjacent clock phases were to overlap, a virtual short circuit would be formed between the input of the delay line and the input of the amplifier. An example of such even duty cycle, non-overlapping phases is shown in FIG. 3. Clock generator circuits capable of producing the even duty cycle, non-overlapping clock phases shown in FIG. 3 are well known in the art of analog design. The clock circuits, however, are complicated because of the precise tolerances imposed on the clock phases. Accordingly, a need remains for an analog delay line which does not require such exacting tolerances on the clock generator circuit.